1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a polydiode element which is improved to be resistant to surge or contamination.
2. Description of the Prior Art
A nonvolatile semiconductor device, which requires a high voltage (10 to 20 V in general) for a write/erase operation for a memory cell, has generally required two external power sources (Vpp/Vcc, Vpp: a high voltage of about 12 V). In recent years, however, a single power source Vcc is employed for attaining commonness with other devices. In this case, the nonvolatile semiconductor device is provided in its chip with a built-in circuit for stepping up the power supply voltage Vcc to the high voltage Vpp.
A charge-pump step-up circuit, which is generally employed in an LSI, has various problems. A textbook "Design of CMOS VLSI" (Baifu-Kan, pp. 192 to 193) describes an exemplary charge-pump step-up circuit, its principle and its problems. According to this literature, the charge-pump step-up circuit serially connects a MOS diode with a unit of a capacitance and performs a step-up operation with two clocks of different timing. However, a rectifying device is formed by the MOS diode. The threshold voltage Vth of the MOS diode gradually increases as the number of stages increases due to a substrate bias effect, and hence step-up efficiency is disadvantageously deteriorated with the number of stages.
IEEE International Solid-State Circuits Conference (1995) TA7.2 discloses a charge-pump step-up circuit forming a P-N junction diode on a substrate not by a MOS diode but through a triple well structure of the substrate. In this case, the efficiency is not deteriorated by the substrate bias effect. However, the process is complicated to increase the cost due to formation of the triple well structure. Further, the capacitance between an N well and the substrate serves as a parasitic capacitance due to formation on the substrate, to disadvantageously deteriorate the efficiency.
FIG. 38 shows an EEPROM comprising a charge-pump step-up circuit utilizing a P-N junction diode (hereinafter referred to as a polydiode element) 2 employing polysilicon, which is disclosed in (Lateral Polysilicon p-n Diodes (J. Electrochem. Soc., Vol. 125, October 1978, p. 1648). This EEPROM also appears in IEEE J. Solid-State Circuits, Vol. SC-16, June 1981, p. 195 and IEEE Trans. Electron Devices, Vol. ED-27, July 1980, p. 1211.
Referring to FIG. 38, the polydiode element 2 is formed on an SiO.sub.2 film 1. An interlayer isolation film 3 is formed on the SiO.sub.2 film 1, to cover the polydiode element 2. Aluminum wires 4 are connected to a P-type layer and an N-type layer of the polydiode element 2 through contact holes provided in the interlayer isolation film 3.
In case of employing the polydiode element 2 shown in FIG. 38, no problem of a substrate bias effect or a parasitic capacitance is caused dissimilarly to the case of employing a MOS diode or a P-N diode formed on a substrate. However, the aluminum wires 4 are directly electrically in contact with the polydiode element 2 to cause reaction on the interfaces therebetween, to disadvantageously result in dispersion of contact resistance as well as dispersion of the characteristics of the polydiode element 2. Further, such a conventional polydiode element 2 is not resistant to electrical noise such as surge. Further, the conventional polydiode element 2 shown in FIG. 38 is not resistant to contamination.